Overview
AMD is a sponsor of the 16th IEEE International Symposium on High-Performance Computer Architecture.
Date: January 9-14, 2010
Location: National Science Seminar Complex, Indian Institute of Science, Bangalore, India
Conference web site: http://www.hpcaconf.org/
Workshop (proposed)
Date: January 10, 2010 (afternoon session)
Title: Tutorial on Software Performance Optimization
Description:
We will cover a development cycle for software performance optimization using open source performance analysis and compiler tools. These tutorials are directed at the extended performance software/computer architecture community at large including developers who aim to optimize their code for performance in x86 architectures, open source contributors and researchers in computer architecture. There will be two sessions conducted over a day.
Session 1: Profile based performance analysis:
This session will be an introduction to program profiling using hardware performance monitoring counters (PMC). Most modern processors have PMC’s, which can capture a wealth of data about the processor’s performance. We will use event counter based profiling to show how to identify hot loops and hot functions in code and to understand the program’s interaction with the hardware, for example, program’s data/instruction cache and TLB behavior or specific issues in the program data access like misaligned accesses and many others. We will use the open source AMD Code Analyst tool to illustrate [CA2008] a performance analysis workflow. Depending on the number of participants and if local arrangements permit, we could make this into a hands on tutorial.
Session 2: Tuning program performance using open64 compiler:
This tutorial will introduce Open64 compiler’s internals. The x86 Open64 compiler suite simplifies and accelerates development and tuning of applications [AMDSTAFF2009] [AMDSUITE2009]. In this session we will introduce the overall architecture of the compiler and demonstrate how to add a new optimization. We will discuss one or more of the core intermediate forms used in the compiler, for example WHIRL, SSA form, interprocedural call graph, ISA machine description and other components in the compiler. We will include how-to walkthroughs with compiler code snippets in our discussion which, for example, will describe how to iterate over natural loops or dominator tree or interprocedural call graph. This tutorial will provide participants with the knowledge of the compiler and enable them to add their optimization to the suite.
We will also demonstrate some of the existing optimization capabilities of the compiler, for instance, some of the parallelizing/vectorizing features, interprocedural analysis/optimization features and show how to leverage the existing features with examples.
Total duration of the tutorials: 1/2 day
Organizers:
- Mike Goddard, Senior Director and Chief Engineer, Products Group, AMD Inc.
- Ramshankar Ramanarayanan, Member of Technical Staff, Platform Software Organization India, AMD Inc.
- Vikrant Kumar, Senior Software Engineer, Platform Software Organization India, AMD Inc.
Bibliography
[CA2008] An introduction to analysis and optimization with AMD CodeAnalyst™ Performance Analyzer, Paul J. Drongowski, AMD CodeAnalyst Team, AMD Boston design center, September 2008.
http://developer.amd.com/Assets/Introduction_to_CodeAnalyst.pdf
[AMDSUITE2009] x86 Open64 Compiler Suite
http://developer.amd.com/cpu/open64/onlinehelp/pages/x86_open64_help.htm
Compiler available for download at: http://developer.amd.com/cpu/open64/Pages/default.aspx
[AMDSTAFF2009] Optimizing x86 Applications with Open64: Using the Open64 Compiler Suite 4.2.2, AMD Staff Engineer, August 2009
http://developer.amd.com/documentation/articles/pages/optimizewithopen64.aspx
Biographies of organizers:
Michael Goddard
Senior Director and Chief Engineer, Products Group, AMD
As the chief engineer of the product engineering group, Michael Goddard provides leadership in developing the technology and product strategy for product group’s research and development efforts and execution of platform delivery through ecosystem partners.
Michael is currently operating from India, on an assignment to drive the ultra-low power and low-cost clients products design group.
Michael has been with AMD since 1988 and has previously served as Senior Director of the AMD Performance Center of Excellence, responsible for the performance modeling teams, architecture extensions team, power analysis lab, and performance labs for the mobile, desktop and server businesses. Earlier in his career, he was a Senior Member of Technical Staff on the microprocessor design team and spent 10 years as a key contributor helping AMD develop its family of x86 microprocessor products. Michael has also spent three years in Europe helping software developers analyze and optimize their code for the AMD Athlon™ family of processors.
Goddard earned a bachelor’s degree in Electrical and Computer Engineering from Carnegie Mellon University, and an MBA from the University of Texas, Austin. He holds more than 15 patents in various areas of computer architecture.
Ramshankar Ramanarayanan
Member of Technical Staff, Platform Software, AMD
Ramshankar Ramanarayanan is a Member of Technical Staff at AMD. He has been with AMD’s compiler team since 2007. He is working on optimization technology for high-performance compilation for AMD multicore architectures. His primary research interests include compiler optimization and program analysis, computer architecture, multicore systems and parallel processing. He received his Bachelor of Engineering degree in Electronics and Communication Engineering at University of Madras in 1999 and Masters in Electrical and Computer Engineering from University of Massachusetts, Amherst in 2003.
Vikrant Kumar
Senior Software Engineer, Platform Software, AMD
Vikrant Kumar is a Senior Software Engineer at AMD. He has been with AMD’s compiler team since 2007. He is working on optimization technology for high-performance compilation for AMD multi-core architectures. His primary research interests include parallel processing, computer architecture, multicore systems and program analysis and compiler optimization. He received his Bachelor of Technology degree in Aerospace Engineering from Indian Institute of Technology, Kanpur in 2002.
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