AMD Opteron™ and AMD Athlon™ 64 processors are well known for their ACPI compliant power management capabilities that allow the processor cores to independently adjust the performance state and power state, and result is significant power savings.

The performance state is known as the P-state and is defined as the valid operating combinations of processor core voltage and frequency; and, as a result changes, the rate at which Time Stamp Counter (TSC) increments. The power state is known as the C-state when an operating system can place a processor in idle state, with C1-state being the most useful and interesting power state. C1 clock ramping feature has been enabled in recent multi-core systems, which significantly reduces the power consumption of an idle core that issues a halt (HLT) instruction, but also causes the TSC to increment very slowly while in halt.

The P-state and C-state changes can affect the TSC and can result in TSC drift amongst the processor cores. The drift occurs only when the operating system uses TSC as the time keeping source. TSC drift can occur on K8 AMD multi-processor platforms and single-processor dual-core platforms as they do not provide frequency independent TSC. This drift does not occur on single-processor single-core platforms for obvious reasons.