Translation lookaside buffers help the processor map virtual addresses to physical addresses. They hold the most recently used page mapping information in fast, chip-resident memory to speed up address translation.

Certain versions of the AMD Athlon 64 and AMD Opteron microarchitecture provides separate TLBs for instructions and data. Each TLB is a two-level structure with a level 1 (L1) TLB and a larger, level 2 (L2) TLB. (See the software optimization guide for more details.) Each TLB entry describes the mapping for a single page. Since the capacity of each TLB level is limited, there are only so many pages that can be touched directly without incurring a TLB miss.

When an L1 TLB miss occurs, page mapping information is sought in the corresponding L2 TLB. If found, the entry is written to the L1 TLB. If not found, the Page Table Walker is invoked to find the mapping information in the memory-resident page tables. A refill from the L2 TLB is much cheaper than a refill from L2 cache or system memory (2 cycles versus 50 cycles or more in the worst case when page information is brought in from system memory.)

TLB behavior favors programs with good spatial and temporal locality and with a small virtual memory working set.