Barcelona's Innovative Architecture Is Driven by a New Shared Cache

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Quad-Core AMD Opteron™ Processors

Barcelona's Innovative Architecture Is Driven by a New Shared Cache

> > > Barcelona's Innovative Architecture Is Driven by a New Shared Cache

Five years ago, AMD shook up the x86 processor by putting a memory controller directly on-chip. Now, AMD breaks new ground again with an innovative cache strategy. Inside AMD's three-tier cache design.

Overview

Anderson Bailey

8/14/2007

When it comes to innovations in x86 designs, AMD has been a leader for many years, especially in features that provide topflight performance: on-chip memory controllers, HyperTransport™ technology links, 64-bit extensions, and multiple cores.

The Barcelona family of x86 processors to be released in August by AMD provides another host of innovations. And none will be more visible than AMD's radical redesign of the cache hierarchy.

This article discusses the three levels of cache in Barcelona and the unique ways in which they interact. Only a basic understanding of processor caches is needed to follow along.

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